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FDS5672 N-Channel PowerTrench(R) MOSFET
July 2005
FDS5672 N-Channel PowerTrench(R) MOSFET
60V, 12A, 10m Features
rDS(ON) = 10m VGS = 10V, ID = 12A , rDS(ON) = 14m VGS = 6V, ID = 10A , High performance trench technology for extremely low rDS(ON) Low gate charge High power and current handling capability
General Description
This N-Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low rDS(ON) and fast switching speed.
Applications
DC/DC converters
Branding Dash
5
5
4 3 2 1
6 7
1 2 3 4
8
SO-8
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FDS5672 N-Channel PowerTrench(R) MOSFET
MOSFET Maximum Ratings TC = 25C unless otherwise noted
Symbol VDSS VGS ID Parameter Drain to Source Voltage Gate to Source Voltage Drain Current Continuous (TC = 25 oC, VGS = 10V, RJA = 50oC/W) Continuous (TC = 25 C, VGS = 6V, RJA = 50 C/W) Pulsed EAS PD TJ, TSTG Single Pulse Avalanche Energy (Note 1) Power dissipation Derate above 25oC Operating and Storage Temperature
o o
Ratings 60 20 12 10 Figure 4 245 2.5 20 -55 to 150
Units V V A A mJ W mW/oC
o
C
Thermal Characteristics
RJC RJA RJA Thermal Resistance Junction to Case (Note 2) Thermal Resistance Junction to Ambient at 10 seconds (Note 3) Thermal Resistance Junction to Ambient at 1000 seconds (Note 3) 25 50 85
oC/W oC/W o
C/W
Package Marking and Ordering Information
Device Marking FDS5672 Device FDS5672 Package SO-8 Reel Size 330mm Tape Width 12mm Quantity 2500 units
Electrical Characteristics TC = 25C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BVDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250A, VGS = 0V VDS = 50V VGS = 0V VGS = 20V TC = 150oC 60 1 250 100 V A nA
On Characteristics
VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250A ID = 12A, VGS = 10V rDS(ON) Drain to Source On Resistance ID = 10A, VGS = 6V, ID = 12A, VGS = 10V, TC = 150oC 2 0.0088 0.012 0.016 4 0.010 0.014 0.023 V
Dynamic Characteristics
CISS COSS CRSS RG Qg(TOT) Qg(TH) Qgs Qgs2 Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance Total Gate Charge at 10V Threshold Gate Charge Gate to Source Gate Charge Gate Charge Threshold to Plateau Gate to Drain "Miller" Charge VDS = 25V, VGS = 0V, f = 1MHz VGS = 0.5V, f = 1MHz VGS = 0V to 10V VGS = 0V to 2V VDD = 30V ID = 12A Ig = 1.0mA 2200 410 130 1.4 34 4.2 9.4 5.2 9.3 45 5.5 pF pF pF nC nC nC nC nC
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FDS5672 N-Channel PowerTrench(R) MOSFET
Resistive Switching Characteristics (VGS = 10V)
tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time VDD = 30V, ID = 12A VGS = 10V, RGS = 9.1 13 20 35 14 50 64 ns ns ns ns ns ns
Drain-Source Diode Characteristics
VSD trr QRR Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ISD = 12A ISD = 6A ISD=12A, dISD/dt = 100A/s ISD=12A, dISD/dt = 100A/s 1.25 1.0 39 40 V V ns nC
Notes: 1: Starting TJ = 25C, L = 1mH, IAS = 22A, VDD = 60V, VGS = 10V. 2: RJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RJC is guaranteed by design while RJA is determined by the user's board design. 3: RJA is measured with 1.0 in2 copper on FR-4 board.
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FDS5672 N-Channel PowerTrench(R) MOSFET
Typical Characteristics TC = 25C unless otherwise noted
1.2 15
POWER DISSIPATION MULTIPLIER
1.0 ID, DRAIN CURRENT (A)
12 VGS = 10V 9
0.8
0.6
6
0.4
0.2
3
0 0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC)
0 25 50 75 100 125 150 TA, AMBIENT TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs Ambient Temperature
2 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01
Figure 2. Maximum Continuous Drain Current vs Ambient Temperature
ZJA, NORMALIZED THERMAL IMPEDANCE
0.1
PDM 0.01 SINGLE PULSE t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA
0.001 10-5
10-4
10-3
10-2
10-1
100
101
102
103
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
1100 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION IDM, PEAK CURRENT (A) TA = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 150 - TA 125 100
VGS = 10V
10 10-5 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101 102 103
Figure 4. Peak Current Capability
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FDS5672 N-Channel PowerTrench(R) MOSFET
Typical Characteristics TC = 25C unless otherwise noted
400 100s IAS, AVALANCHE CURRENT (A) 100 ID, DRAIN CURRENT (A) 1ms 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) SINGLE PULSE TJ = MAX RATED TA = 25oC 0.1 0.1 1 10 70 VDS, DRAIN TO SOURCE VOLTAGE (V) 50 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 10 STARTING TJ = 25oC
10ms
1
STARTING TJ = 150oC 1 0.1 1 10 100 tAV, TIME IN AVALANCHE (ms)
Figure 5. Forward Bias Safe Operating Area
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching Capability
25 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V ID, DRAIN CURRENT (A)
25 VGS = 6V 20 VGS = 5V
20 ID , DRAIN CURRENT (A)
15 TJ = 150oC 10 TJ = 25oC 5 TJ = -55oC
15 VGS = 10V 10 VGS = 4.5V
5
0 3.0 3.5 4.0 4.5 5.0 5.5 VGS , GATE TO SOURCE VOLTAGE (V)
0 0 0.2 0.4
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TA = 25oC 0.6 0.8 1.0
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Transfer Characteristics
15.0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE
Figure 8. Saturation Characteristics
2.0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
DRAIN TO SOURCE ON RESISTANCE (m )
VGS = 6V 12.5
1.5
10.0 VGS = 10V 7.5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 5.0 0 3 6 ID, DRAIN CURRENT (A) 9 12
1.0
VGS = 10V, ID = 12A 0.5 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
Figure 9. Drain to Source On Resistance vs Drain Current
Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature
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FDS5672 N-Channel PowerTrench(R) MOSFET
Typical Characteristics TC = 25C unless otherwise noted
1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250A 1.1 NORMALIZED GATE THRESHOLD VOLTAGE 1.10 ID = 250A 1.05
1.0
0.9
1.00
0.8
0.95
0.7
0.6 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
0.90 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC)
Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature
6000
Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature
10 VGS , GATE TO SOURCE VOLTAGE (V)
CISS = CGS + CGD
VDD = 50V 8
C, CAPACITANCE (pF)
1000
COSS CDS + CGD
6
CRSS = CGD
4
100 VGS = 0V, f = 1MHz 40 0.1 1 10 60 VDS , DRAIN TO SOURCE VOLTAGE (V)
2
0 0 5 10 15
WAVEFORMS IN DESCENDING ORDER: ID = 12A ID = 1A 20 25 30 35
Qg, GATE CHARGE (nC)
Figure 13. Capacitance vs Drain to Source Voltage
Figure 14. Gate Charge Waveforms for Constant Gate Currents
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FDS5672 N-Channel PowerTrench(R) MOSFET
Test Circuits and Waveforms
VDS tP L IAS VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP 0V RG VDD
+
BVDSS
VDS
VDD
IAS 0.01
0 tAV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
VDS
VDD
Qg(TOT) VDS
L VGS = 10V VGS
+
VDD DUT Ig(REF) 0 Qg(TH)
VGS VGS = 2V Qgs2 Qgs Ig(REF) 0 Qgd
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON td(ON) RL VDS 90% tr
tOFF td(OFF) tf 90%
VGS
+
VDD DUT 0
10%
10%
90% VGS 50% PULSE WIDTH 50%
RGS
VGS
0
10%
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
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FDS5672 N-Channel PowerTrench(R) MOSFET
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
(T -T ) JM A P DM = -----------------------------R JA
maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2. The area, in square inches is the top copper area including the gate and source pads. R JA = 64 + -------------------------------
26 0.23 + Area
(EQ. 2)
(EQ. 1) The transient thermal impedance (ZJA) is also effected by varied top copper board area. Figure 22 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas. Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1.
200 RJA = 64 + 26/(0.23+Area)
In using surface mount devices such as the SO8 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 21 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized
150 COPPER BOARD AREA - DESCENDING ORDER 0.04 in2 0.28 in2 0.52 in2 0.76 in2 1.00 in2
RJA (oC/W)
150
100
50 0.001 0.01 0.1 1 AREA, TOP COPPER AREA (in2) 10
Figure 21. Thermal Resistance vs Mounting Pad Area
ZJA, THERMAL IMPEDANCE (oC/W)
120
90
60
30
0 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) 102 103
Figure 22. Thermal Impedance vs Mounting Pad Area
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FDS5672 N-Channel PowerTrench(R) MOSFET
PSPICE Electrical Model
.SUBCKT FDS5672 2 1 3 ; Ca 12 8 7e-10 Cb 15 14 7e-10 Cin 6 8 2.2e-10 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 67 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 1.23e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 0.18e-9 RLgate 1 9 12.3 RLdrain 2 5 10 RLsource 3 7 1.8 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 1e-3 Rgate 9 20 1.4 RSLC1 5 51 RSLCMOD 1.0e-6 RSLC2 5 50 1.0e3 Rsource 8 7 RsourceMOD 3.2e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),2.5))} .MODEL DbodyMOD D (IS=4.5E-12 RS=4.7e-3 TRS1=1.5e-3 TRS2=2e-5 + CJO=1.6e-9 M=0.55 TT=1.8e-8 XTI=3.0) .MODEL DbreakMOD D (RS=2.5 TRS1=1.0e-3 TRS2=1e-6) .MODEL DplcapMOD D (CJO=6.0e-10 IS=1.0e-30 N=10 M=0.45) .MODEL MmedMOD NMOS (VTO=3.35 KP=4 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.4) .MODEL MstroMOD NMOS (VTO=3.93 KP=50 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=2.82 KP=0.04 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=14 RS=0.1) .MODEL RbreakMOD RES (TC1=7e-4 TC2=-1.3e-7) .MODEL RdrainMOD RES (TC1=1.0e-4 TC2=1e-5) .MODEL RSLCMOD RES (TC1=1.0e-2 TC2=1e-7) .MODEL RsourceMOD RES (TC1=1.0e-2 TC2=1.0e-6) .MODEL RvthresMOD RES (TC1=-3.9e-3 TC2=-1.4e-5) .MODEL RvtempMOD RES (TC1=-4e-3 TC2=2e-7) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4.0 VOFF=-2.0) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=-4.0) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=0) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0 VOFF=-0.5) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
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GATE 1 RLGATE CIN
rev June 2005
LDRAIN DPLCAP 10 RSLC1 51 ESLC 50 RLDRAIN DBREAK 11 + 17 EBREAK 18 MWEAK MMED MSTRO LSOURCE 8 RSOURCE RLSOURCE S1A 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT VBAT + 22 15 17 RBREAK 18 RVTEMP 19 7 SOURCE 3 5 DRAIN 2
RSLC2
5 51 ESG + LGATE EVTEMP RGATE + 18 22 9 20 6 6 8 EVTHRES + 19 8 -
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RDRAIN 21 16
DBODY
FDS5672 N-Channel PowerTrench(R) MOSFET
SABER Electrical Model
REV June 2005 ttemplate FDS5672 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=4.5e-12,rs=4.7e-3,trs1=1.5e-3,trs2=2e-5,cjo=1.6e-9,m=0.55,tt=1.8e-8,xti=3.0) dp..model dbreakmod = (rs=2.5,trs1=1e-4,trs2=1e-6) dp..model dplcapmod = (cjo=6.0e-10,isl=10.0e-30,nl=10,m=0.45) m..model mmedmod = (type=_n,vto=3.35,kp=4,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=3.93,kp=50,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=2.82,kp=0.04,is=1e-30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4.0,voff=-2.0) sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2.0,voff=-4.0) DPLCAP 5 sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.5,voff=0) 10 sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0,voff=-0.5) c.ca n12 n8 = 7e-10 RSLC1 51 c.cb n15 n14 = 7e-10 RSLC2 c.cin n6 n8 = 2.2e-9
ISCL
LDRAIN DRAIN 2 RLDRAIN
dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 67 spe.eds n14 n8 n5 n8 = 1 GATE spe.egs n13 n8 n6 n8 = 1 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1 l.lgate n1 n9 = 1.23e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 0.18e-9 res.rlgate n1 n9 = 12.3 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 1.8
CA LGATE
ESG + EVTEMP RGATE + 18 22 9 20 6 6 8 EVTHRES + 19 8
50 RDRAIN 21 16
DBREAK 11 DBODY MWEAK MMED EBREAK + 17 18 -
RLGATE CIN
MSTRO 8
LSOURCE 7 RLSOURCE
SOURCE 3
RSOURCE S1A 12 S1B 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT VBAT + 22 15 17 RBREAK 18 RVTEMP 19
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=7e-4,tc2=-1.3e-7 res.rdrain n50 n16 = 1e-3, tc1=1e-4,tc2=1e-5 res.rgate n9 n20 = 1.4 res.rslc1 n5 n51 = 1e-6, tc1=1e-2,tc2=1e-7 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 3.2e-3, tc1=1e-2,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-3.9e-3,tc2=-1.4e-5 res.rvtemp n18 n19 = 1, tc1=-4e-3,tc2=2e-7 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 2.5)) } }
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FDS5672 N-Channel PowerTrench(R) MOSFET
SPICE Thermal Model
REV June 2005 FDS5672_JA Junction Ambient Copper Area = 1sq.in CTHERM1 TH 8 2e-3 CTHERM2 8 7 5e-3 CTHERM3 7 6 1e-2 CTHERM4 6 5 4e-2 CTHERM5 5 4 9e-2 CTHERM6 4 3 2e-1 CTHERM7 3 2 1 CTHERM8 2 TL 3 RTHERM1 TH 8 1e-1 RTHERM2 8 7 5e-1 RTHERM3 7 6 1 RTHERM4 6 5 5 RTHERM5 5 4 8 RTHERM6 4 3 12 RTHERM7 3 2 18 RTHERM8 2 TL 25
RTHERM1 8 CTHERM1 th JUNCTION
RTHERM2 7
CTHERM2
RTHERM3 6
CTHERM3
RTHERM4
CTHERM4 5
SABER Thermal Model
SABER thermal model FDS5672 Copper Area = 1sq.in template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 =2e-3 ctherm.ctherm2 8 7 =5e-3 ctherm.ctherm3 7 6 =1e-2 ctherm.ctherm4 6 5 =4e-2 ctherm.ctherm5 5 4 =9e-2 ctherm.ctherm6 4 3 =2e-1 ctherm.ctherm7 3 2 =1 ctherm.ctherm8 2 tl =3 rrtherm.rtherm1 th 8 =1e-1 rtherm.rtherm2 8 7 =5e-1 rtherm.rtherm3 7 6 =1 rtherm.rtherm4 6 5 =5 rtherm.rtherm5 5 4 =8 rtherm.rtherm6 4 3 =12 rtherm.rtherm7 3 2 =18 rtherm.rtherm8 2 tl =25 }
RTHERM5 4 CTHERM5
RTHERM6 3
CTHERM6
RTHERM7 2
CTHERM7
RTHERM8
CTHERM8
tl
AMBIENT
T ABLE 1. THERMAL MODELS 0.04 in2 1.2e-1 0.5 1.3 26 39 55 0.28 in2 1.5e-1 1.0 2.8 20 24 38.7 0.52 in2 2.0e-1 1.0 3.0 15 21 31.3 0.76 in2 2.0e-1 1.0 3.0 13 19 29.7 1.0 in2 2.0e-1 1.0 3.0 12 18 25
COMPONANT CTHERM6 CTHERM7 CTHERM8 RTHERM6 RTHERM7 RTHERM8
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FDM3622 N-Channel PowerTrench(R) MOSFET
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2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Preliminary
No Identification Needed
Full Production
Obsolete
Not In Production
(c)2005 Fairchild Semiconductor Corporation FDS5672 Rev. A
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